DRAM Capacitor Module

ABSTRACT

Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. application Ser. No. 16/826,597, filed on Mar. 23, 2020, which claims priority to U.S. Provisional Application No. 62/823,977, filed Mar. 26, 2019, the entire disclosures of which are hereby incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the present invention pertain to the field of semiconductor device manufacturing and methods for device patterning. In particular, embodiments pertain to the self-aligned DRAM devices and their manufacturing methods.

BACKGROUND

Electronic devices, such as personal computers, workstations, computer servers, mainframes and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. There are two major types of random-access memory cells, dynamic and static, which are well-suited for use in electronic devices. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short periods of time. Static random-access memories (SRAM) are so named because they do not require periodic refreshing.

DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. The output voltage of a DRAM cell is proportional to the capacitance value of the storage capacitor of the DRAM cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. The storage capacitor can be implemented in a trench-type or a stack-type. The trench-type capacitor is formed by forming a trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface; however, the trench formation becomes difficult as the feature size decreases. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with nonarray devices.

DRAM cells and circuits may be produced using semiconductor lithography. Modern trends in DRAM production include scaling DRAMs to ever smaller lithography sizes. As sizes are reduced, it becomes more difficult to maintain reliability and performance as lithography error rates increase. Thus, there is a need for DRAMs that are scalable while maintaining reliability and performance.

SUMMARY

One or more embodiments of the disclosure are directed to electronic devices and to methods of manufacturing the electronic devices. In one embodiment, a method of manufacturing a DRAM capacitor comprises: selectively etching a capacitor bottom contact from a substrate comprising the capacitor bottom contact and a first dielectric material to form a recess; forming pillars in the recess on the capacitor bottom contact; depositing a second dielectric material on the first dielectric material; selectively removing the pillars to form capacitor memory holes; conformally depositing a first conductive material in the capacitor memory hole; conformally depositing a third dielectric material on the first conductive material; and depositing a second conductive material on the third dielectric material to form the DRAM capacitor, wherein the capacitor bottom contact is self-aligned with the first conductive material.

In one embodiment, a DRAM capacitor comprises: a capacitor bottom contact and a first dielectric material on a substrate; a second dielectric material on the first dielectric material; a fourth dielectric material on the second dielectric material; a capacitor memory channel formed through the fourth dielectric material and the second dielectric material; and a capacitor formed in the memory channel, wherein the capacitor is self-aligned with the capacitor bottom contact.

In one an embodiment, a method of manufacturing a DRAM capacitor comprises: providing a substrate having a capacitor bottom contact and a first dielectric material; selectively etching the capacitor bottom contact to form a first recess; depositing a conformal liner in the first recess; selectively depositing a first seed layer in the first recess on the capacitor bottom contact; forming first pillars from the first seed layer; depositing a second dielectric material on the first dielectric material to form an overburden of the second dielectric material; removing the overburden of the second dielectric material such that a top surface of the second dielectric material is substantially coplanar with a top surface of the first pillars; selectively etching the first pillars to form a second recess; selectively depositing a second seed layer in the second recess on the first pillars; forming second pillars from the second seed layer; depositing a fourth dielectric material on the second dielectric material to form an overburden of the third dielectric material; removing the overburden of the fourth dielectric material such that a top surface of the fourth dielectric material is substantially coplanar with a top surface of the second pillars; selectively removing the first pillars and the second pillars to form capacitor memory holes; removing the conformal liner; and forming a capacitor in the capacitor memory holes by conformally depositing a first conductive material in the capacitor memory holes, conformally depositing a third dielectric material on the first conductive material, and depositing a second conductive material on the third dielectric material to form the DRAM capacitor, wherein the capacitor is self-aligned with capacitor bottom contact.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 illustrates a circuit diagram of a DRAM cell block in accordance with the prior art;

FIG. 2 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 3 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 4 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 5 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 6 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 7 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 8 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 9 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 10A illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 10B illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 10C illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 10D illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 10E illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 11 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 12 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 13 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 14 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 15 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 16 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 17 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 18 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 19A illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 19B illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure;

FIG. 20 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure; and

FIG. 21 illustrates a cross-section view of an electronic device according to one or more embodiments of the disclosure.

DETAILED DESCRIPTION

Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

A “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such under-layer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

As used in this specification and the appended claims, the terms “precursor”, “reactant”, “reactive gas” and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

As used herein, the term “dynamic random access memory” or “DRAM” refers to a memory cell that stores a datum bit by storing a packet of charge (i.e., a binary one), or no charge (i.e., a binary zero) on a capacitor. The charge is gated onto the capacitor via an access transistor, and sensed by turning on the same transistor and looking at the voltage perturbation created by dumping the charge packet on the interconnect line on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. The DRAM device, as illustrated in FIG. 1, is formed of an array of DRAM cells. The rows on access transistors are linked by word lines 52 a, 52 b, and the transistor inputs/outputs are linked by bit lines 54 a, 54 b, and 54 c. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to 3-D structures which have diverged into “stack” capacitors with both plates above the substrate, and “trench” capacitors using an etched cavity in the substrate as the common plate.

In one or more embodiments, memory devices, DRAM capacitors in particular, are provided where the capacitor is advantageously self-aligned with the capacitor bottom contact, resulting in a uniform critical dimension, better bottom contact, and increased height of the capacitor.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing.

FIGS. 2 through 21 are cross-sectional views illustrating a memory device 100, a DRAM capacitor for example, according to one or more embodiments. With reference to FIGS. 2 and 3, in one or more embodiments, a capacitor bottom contact 104 is selectively etched from a substrate comprising the capacitor bottom contact 104 and a first dielectric material 102 to form a recess 106.

As used herein, the term “dielectric material” refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric layer comprises one or more of oxides, carbon doped oxides, silicon oxide (SiO), porous silicon dioxide (SiO₂), silicon oxide (SiO), silicon nitride (SiN), silicon oxide/silicon nitride, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH).

In one or more embodiments, the first dielectric material can be any suitable material known to the skilled artisan. In one or more embodiments, the first dielectric material 102 comprises silicon oxide or silicon nitride.

In one or more embodiments, the capacitor bottom contact 104 can be any suitable material known to the skilled artisan. In one or more embodiments, the capacitor bottom contact 104 comprises one or more of a metal, a metal silicide, poly-silicon, or EPI-silicon. In one or more embodiments, the capacitor bottom contact 104 is doped by either N type dopants or P type dopants in order to reduce contact resistance. In one or more embodiments, the metal of the capacitor bottom contact 104 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

In one or more embodiments, as illustrated in FIG. 4, a conformal liner 108 is optionally deposited on the first dielectric material 102 and the recessed capacitor bottom contact 104. In one or more embodiments, the optional liner 108 can be conformal liner 108. In one or more embodiments, the conformal liner 108 is selected from a conductive liner or a dielectric liner. In one or more embodiments, the conformal liner 108 can be any suitable metal liner material known to the skilled artisan. In one or more embodiments, the conformal liner 108 comprises a metal nitride film. In some embodiments, the conformal liner 108 comprises one or more of tungsten nitride, tantalum nitride, or titanium nitride.

As used herein, a layer or a liner which is “substantially conformal” refers to a layer where the thickness is about the same throughout (e.g., on the dielectric material 102, on the sidewalls of the recess 106, and on the recessed capacitor bottom contact 104). A layer which is substantially conformal varies in thickness by less than or equal to about 5%, 2%, 1% or 0.5%.

Referring to FIG. 5, the conformal liner 108 is removed from the top surface of the dielectric material 102. In other embodiments, the conformal liner 108 is not present. Referring to FIGS. 6 and 7, pillars 112 are formed in the recess 106 on the capacitor bottom contact 104.

In one or more embodiments, selective pillar growth technique is used to grow pillars 112 on the capacitor bottom contact 104. Pillars 112 are formed on the capacitor bottom contact 104. FIG. 7 illustrates pillars 112 being grown on an optional liner 108. Referring to FIG. 6, in one or more embodiments, self-aligned selective growth pillars 112 are formed using a seed gapfill layer 110, optionally on the liner 108, on the recessed conductive lines of the capacitor bottom contact 104.

As used herein, the term “self-aligned growth pillars” refers to columns or towers of a metal (e.g. tungsten) that are used to form self-aligned capacitor memory holes. The self-aligned growth pillars have a height H₁ of about 5 angstroms (Å) to about 10 microns (μm) that extends above the top surface 105 of the electronic device 100. The width W₁ of the self-aligned growth pillars is in a range of about 0.5 nm to about 2000 nm.

As shown in FIG. 7, the pillars 112 extend substantially orthogonally from the top surface 105 of the electronic device 100. As shown in FIG. 7, the pillars 112 extend along the same direction as the conductive lines of the capacitor bottom contact 104, and are separated by gaps 107.

With reference to FIG. 6, in one or more embodiments, a seed gapfill layer 110 is deposited on the capacitor bottom contact 104. In one embodiment, the seed gapfill layer 110 is a self-aligned selective growth seed film. In one or more embodiments, the seed gapfill layer 110 is deposited on capacitor bottom contact 104 on the top surface of the recessed conductive lines. In one or more embodiments, the seed gapfill layer 110 is a tungsten (W) layer, or other seed gapfill layer to provide selective growth pillars 112. In some embodiments, the seed gapfill layer 110 is a metal film or a metal containing film. Suitable metal films include, but are not limited to, films including one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, the seed gapfill layer 110 is a tungsten (W) seed gapfill layer.

In one or more embodiments, the seed gapfill layer 110 is deposited using one or more deposition techniques, such as but not limited to ALD, CVD, PVD, MBE, MOCVD, spin-on or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one or more embodiments, portions of the seed gapfill layer 110 above the capacitor bottom contact 104 are expanded for example, by oxidation, nitridation, or other process to grow pillars 112. In one embodiment, the seed gap fill layer 112 is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing seed gapfill layer 110 to metal oxide pillars 112. In one or more embodiments, pillars 112 include an oxide of one or more metals listed above. In more specific embodiment, pillars 112 include tungsten oxide (e.g., WO, WO₃ and other tungsten oxide).

The oxidizing agent can be any suitable oxidizing agent including, but not limited to, O₂, O₃, N₂O, H₂O, H₂O₂, CO, CO₂, NH₃, N₂/Ar, N₂/He, N₂/Ar/He or any combination thereof. In some embodiments, the oxidizing conditions comprise a thermal oxidation, plasma enhanced oxidation, remote plasma oxidation, microwave and radio-frequency oxidation (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP)).

In one or more embodiments, the pillars 112 are formed by oxidation of the seed gapfill layer 110 at any suitable temperature depending on, for example, the composition of the seed gapfill layer 110 and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25° C. to about 800° C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150° C.

In one or more embodiments, deposition or formation of a material may be performed by any suitable technique known to the skilled artisan including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. Referring to FIG. 8, a second dielectric material 114 is deposited on the first dielectric material 102 and on the top surface 113 of the pillars 112. In one or more embodiments, the second dielectric material 114 can be any suitable material known to the skilled artisan. In one or more embodiments, the second dielectric material 114 comprises silicon oxide or silicon nitride. In one or more embodiments, the second dielectric material 114 is the same material as the first dielectric material 102.

As illustrated in FIG. 8, in one or more embodiments, an overburden 116 of the second dielectric material 114 is formed. Referring to FIG. 9, the overburden 116 may be removed by any suitable technique known to one of skill in the art including, but not limited to, chemical mechanical planarization (CMP), dry etching, or wet etching. In one or more embodiments, when the overburden 116 of the second dielectric material 114 is removed, the second dielectric material 114 is substantially coplanar with the top surface 113 of the pillars 112.

Referring to FIG. 10A, in one or more embodiments, the pillars 112 are selectively removed to form capacitor memory holes 118. In one or more embodiments, the capacitor memory holes 118 are self-aligned with the capacitor bottom contact 104. In one or more embodiments, the self-aligned capacitor memory holes 118 have a minimum width that is equal to the width of the self-aligned growth pillars 112.

As shown in FIG. 10A, the pillars 112 are removed selectively to the capacitor bottom contact 104. In one or more embodiments, if the optional conformal liner 108 is a non-conductive liner (e.g. a dielectric liner), it is also removed. In one embodiment, the pillars 112 and liner 108 are removed selectively to the capacitor bottom contact 104. As shown in FIG. 10A, self-aligned capacitor memory holes 118 are formed in the second dielectric material 114 and the first dielectric material 102. As illustrated in FIG. 10A, each self-aligned capacitor memory holes 118 has a bottom that is a top surface of the capacitor bottom contact 104 and opposing sidewalls that include a sidewall portion of first dielectric material 102 and second dielectric material 114. Generally, the aspect ratio of the self-aligned capacitor memory holes 118 refers to the ratio of the depth of the self-aligned capacitor memory holes 118 to the width of the self-aligned capacitor memory holes 118. In one embodiment, the aspect ratio of each self-aligned capacitor memory hole 118 is in an approximate range from about 1:1 to about 200:1. In one or more embodiments, the critical dimensions of the self-aligned capacitor memory holes 118 is substantially uniform along the depth of the self-aligned capacitor memory holes 118. As used herein, the term “substantially uniform” means that the critical dimension at the top of the self-aligned capacitor memory holes 118 is within ±5% of the critical dimension at the bottom of the self-aligned capacitor memory holes 118. In one or more embodiments, the critical dimension variation from the top of the self-aligned capacitor memory holes 118 to the bottom of the self-aligned capacitor memory holes 118 is within 5%.

In one embodiment, the pillars 112 are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the pillars 112 are selectively wet etched by e.g., 5 wt. % of ammonium hydroxide (NH₄OH) aqueous solution at the temperature of about 80 degrees C. In one embodiment, hydrogen peroxide (H₂O₂) is added to the 5 wt. % NH₄OH aqueous solution to increase the etching rate of the pillars 112. In one embodiment, the pillars 112 are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO₃) in a ratio of 1:1. In one embodiment, the pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 3:7 respectively. In one embodiment, the pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 4:1, respectively. In one embodiment, the pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 30%:70%, respectively. In one embodiment, the pillars 112 including tungsten, titanium or both titanium and tungsten are selectively wet etched using NH₄OH and H₂O₂ in a ratio of 1:2, respectively. In one embodiment, the pillars 112 are selectively wet etched using 305 grams of potassium ferricyanide (K₃Fe(CN)₆), 44.5 grams of sodium hydroxide (NaOH) and 1000 ml of water (H₂O). In one embodiment, the pillars 112 are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), HNO₃, sulfuric acid (H₂SO₄), HF, and H₂O₂. In one embodiment, the pillars 112 are selectively wet etched using HF, HNO₃ and acetic acid (AcOH) in a ratio of 4:4:3, respectively. In one embodiment, the pillars 112 are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the pillars 112 are selectively dry etched using chlorine, fluorine, bromine or any combination thereof based chemistries. In one embodiment, the pillars 112 are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO₃ in a ratio of 3:1, respectively. In one embodiment, the pillars 112 are selectively etched using alkali with oxidizers (potassium nitrate (KNOB) and lead dioxide (PbO₂)). In one embodiment, the liner 108 is selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing.

Referring to FIG. 10B, a first conductive material 120 is conformally deposited in the capacitor memory holes 118. The first conductive material 120 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The first conductive material 120 may be any suitable material known to the skilled artisan. In one or more embodiments, the first conductive material 120 comprises one or more of metal mode titanium (MMTi), metal silicide, or highly doped poly-silicon.

As illustrated in FIG. 10B, in one or more embodiments, a layer 122 of the first conductive material 120 is formed on the top surface 121 of the second dielectric material 114. Referring to FIG. 10C, the layer 122 of the first conductive material 120 formed on the top surface 121 of the second dielectric material 114 may be removed by any suitable technique known to one of skill in the art including, but not limited to, chemical mechanical planarization (CMP). In one or more embodiments, when the layer 122 of the first conductive material 120 formed on the top surface 121 of the second dielectric material 114 is removed, the first conductive material 120 is substantially coplanar with the top surface 121 of the second dielectric material 114.

Referring to FIG. 10D, a third dielectric material 124 is conformally deposited in the capacitor memory holes 118 on the first conductive material 120. The third dielectric material 124 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The third dielectric material 124 may be any suitable material known to the skilled artisan. In one or more embodiments, the third dielectric material 124 comprises a high-κ dielectric. In one or more embodiments, the third dielectric material 124 comprises a high-κ dielectric selected from one or more of aluminum oxide, hafnium oxide, or aluminum hafnium oxide (AlHfOx).

Referring to FIG. 10E, in one or more embodiments a second conductive material 126 is deposited on the third dielectric material 124 to form a DRAM capacitor. The second conductive material 126 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The second conductive material 126 may be any suitable material known to the skilled artisan. In one or more embodiments, the second conductive material 126 comprises one or more of poly-silicon, metal, or metal silicide. In one or more embodiments, the poly-silicon may be doped by N-type or P-type dopants. In one or more embodiments, the capacitor bottom contact 104 is self-aligned with the first conductive material 120.

FIGS. 11-21 describe alternative embodiments of the disclosure. FIG. 11 is the same as FIG. 9 and is merely duplicated for convenience. Referring to FIG. 11, the overburden 116 of the second dielectric material 114 has been removed, such that the second dielectric material 114 is substantially coplanar with the top surface 113 of the pillars 112.

With reference to FIG. 12, in one or more embodiments, prior to forming the capacitor memory holes 118, the pillars 112 are selectively etched to form a second recess 128. Referring to FIGS. 13 and 14, second pillars 132 are grown in the second recess 128 on the pillars 112.

Second pillars 132 are formed on the pillars 112. Referring to FIG. 13, in one or more embodiments, self-aligned selective growth pillars 132 are formed using a seed gapfill layer 130 on pillars 112. In one or more embodiments, an optional liner may be deposited in the recess 128 and seed gapfill layer 130 is then deposited on the optional liner to grow the second pillars 132.

In one or more embodiments, the self-aligned growth second pillars 132 have a height H₂ of about 5 angstroms (Å) to about 10 microns (μm) that extends above the top surface 133 of the second dielectric material 114. In one or more embodiments, the height H₂ of the self-aligned growth second pillars 132 is substantially the same as the height H₂ of the self-aligned growth pillars 112. In other embodiments, the height H₂ of the self-aligned growth second pillars 132 is greater than the height H₂ of the self-aligned growth pillars 112. The width W₂ of the self-aligned growth second pillars 132 is in a range of about 0.5 nm to about 2000 nm. In one or more embodiments, the width W₂ of the self-aligned growth second pillars 132 is substantially the same as the width W₁ of the self-aligned growth pillars 112.

As shown in FIG. 14, the second pillars 132 extend substantially orthogonally from the top surface 133 of the second dielectric material 114. As shown in FIG. 14, the second pillars 132 extend along the same direction as the conductive lines of the capacitor bottom contact 104, and are separated by gaps 135.

With reference to FIG. 13, in one or more embodiments, a second seed gapfill layer 130 is deposited on the pillars 112. In one embodiment, the second seed gapfill layer 130 is a self-aligned selective growth seed film. In one or more embodiments, the second seed gapfill layer 130 is deposited on pillars 112 on capacitor bottom contact 104 on the top surface of the recessed conductive lines. In one or more embodiments, optional conformal liner 108 is present on the capacitor bottom contact 104. In one or more embodiments, the second seed gapfill layer 130 is a tungsten (W) layer, or other seed gapfill layer to provide selective growth second pillars 132. In some embodiments, the second seed gapfill layer 130 is a metal film or a metal containing film. Suitable metal films include, but are not limited to, films including one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, the second seed gapfill layer 130 is a tungsten (W) seed gapfill layer.

In one or more embodiments, the second seed gapfill layer 130 is deposited using one or more deposition techniques, such as but not limited to ALD, CVD, PVD, MBE, MOCVD, spin-on or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one or more embodiments, portions of the second seed gapfill layer 130 above the pillars 112 are expanded for example, by oxidation, nitridation, or other process to grow second pillars 132. In one embodiment, the second seed gap fill layer 130 is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing second seed gapfill layer 130 to metal oxide second pillars 132. In one or more embodiments, second pillars 132 include an oxide of one or more metals listed above. In more specific embodiment, second pillars 132 include tungsten oxide (e.g., WO, WO₃ and other tungsten oxide). In one or more embodiments, second pillars 132 comprise the same material as pillars 112. In one or more embodiments, second pillars 132 comprise a material different from pillars 112.

The oxidizing agent can be any suitable oxidizing agent including, but not limited to, O₂, O₃, N₂O, H₂O, H₂O₂, CO, CO₂, NH₃, N₂/Ar, N₂/He, N₂/Ar/He or any combination thereof. In some embodiments, the oxidizing conditions comprise a thermal oxidation, plasma enhanced oxidation, remote plasma oxidation, microwave and radio-frequency oxidation (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP)).

In one or more embodiments, the second pillars 132 are formed by oxidation of the second seed gapfill layer 130 at any suitable temperature depending on, for example, the composition of the second seed gapfill layer 130 and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25° C. to about 800° C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150° C.

With reference to FIG. 15, a fourth dielectric material 134 is deposited on the second dielectric material 114. In one or more embodiments, the fourth dielectric material 134 can be any suitable material known to the skilled artisan. In one or more embodiments, the fourth dielectric material 134 comprises silicon oxide or silicon nitride. In one or more embodiments, the fourth dielectric material 134 is the same material as the second dielectric material 114. In one or more embodiments, the fourth dielectric material 134 is the same material as the first dielectric material 102.

As illustrated in FIG. 15, in one or more embodiments, an overburden 136 of the fourth dielectric material 134 may be formed. Referring to FIG. 16, the overburden 136 may be removed by any suitable technique known to one of skill in the art including, but not limited to, chemical mechanical planarization (CMP), dry etching, or wet etching. In one or more embodiments, when the overburden 136 of the fourth dielectric material 134 is removed, the fourth dielectric material 134 is substantially coplanar with the top surface 135 of the second pillars 132.

While FIGS. 11-16 illustrate two layers of stacked pillars and dielectric layers, the skilled artisan recognizes that the structures and methods described in FIGS. 11-16 may be repeated multiple times to produce more than two stacks of pillars and dielectric layers. In some embodiments, there are three stacks of pillars and dielectric layers. In some embodiments, there are four stacks of pillars and dielectric layers. In some embodiments there are five or more stacks of pillars and dielectric layers. Additional stacks of pillars and dielectric layers will increase the height/depth of the capacitor that may be formed. The method of one or more embodiments advantageously leads to a capacitor self-aligned with the capacitor bottom contact, resulting in a uniform critical dimension and increased height of the capacitor. As used herein, the term “substantially uniform” means that the critical dimension at the top of the self-aligned capacitor memory holes (or capacitor memory channel(s)) is within ±5% of the critical dimension at the bottom of the self-aligned capacitor memory holes (or capacitor memory channel(s)). In one or more embodiments, the critical dimension variation from the top of the self-aligned capacitor memory holes to the bottom of the self-aligned capacitor memory holes is within 5%.

Referring to FIG. 17, in one or more embodiments, the second pillars 132 and pillars 112 are selectively removed to form capacitor memory holes 138. In one or more embodiments, the capacitor memory holes 138 are self-aligned with the capacitor bottom contact 104. In one or more embodiments, the self-aligned capacitor memory holes 138 have a minimum width that is equal to the width of the self-aligned growth pillars 132 and the self-aligned growth pillars 112.

As shown in FIG. 17, the second pillars 132 and pillars 112 are removed selectively to the capacitor bottom contact 104. In one or more embodiments, if the optional conformal liner 108 is a non-conductive liner (e.g. dielectric liner), it is also removed. In one or more embodiments, trimming of the second dielectric material 114 and the fourth dielectric material 134 may be necessary to ensure that the side walls of the capacitor memory holes 138 are substantially uniform. In one embodiment, the second pillars 132, pillars 112 and liner 108 are removed selectively to the capacitor bottom contact 104. As shown in FIG. 17, self-aligned capacitor memory holes 138 are formed in the fourth dielectric material 134, second dielectric material 114, and the first dielectric material 102. As illustrated in FIG. 17, each self-aligned capacitor memory hole 118 has a bottom that is a top surface of the capacitor bottom contact 104 and opposing sidewalls that include a sidewall portion of first dielectric material 102, second dielectric material 114, and fourth dielectric material 134. Generally, the aspect ratio of the self-aligned capacitor memory holes 138 refers to the ratio of the depth of the self-aligned capacitor memory holes 138 to the width of the self-aligned capacitor memory holes 138. In one embodiment, the aspect ratio of each self-aligned capacitor memory hole 138 is in an approximate range from about 1:1 to about 200:1, or from about 10:1 to about 200:1, or from about 200:1 to about 100:1. In one or more embodiments, the critical dimension of the self-aligned capacitor memory holes 138 is substantially uniform along the depth of the self-aligned capacitor memory holes 138. As used herein, the term “substantially uniform” means that the critical dimension at the top of the self-aligned capacitor memory hole 138 is within ±5% of the critical dimension at the bottom of the self-aligned capacitor memory holes 138. In one or more embodiments, the critical dimension variation from the top of the self-aligned capacitor memory holes 138 to the bottom of the self-aligned capacitor memory holes 138 is within 5%.

In one embodiment, the second pillars 132 and pillars 112 are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched by e.g., 5 wt. % of ammonium hydroxide (NH₄OH) aqueous solution at the temperature of about 80 degrees C. In one embodiment, hydrogen peroxide (H₂O₂) is added to the 5 wt. % NH₄OH aqueous solution to increase the etching rate of the second pillars 132 and pillars 112. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO₃) in a ratio of 1:1. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 3:7 respectively. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 4:1, respectively. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using HF and HNO₃ in a ratio of 30%:70%, respectively. In one embodiment, the second pillars 132 and pillars 112 including tungsten, titanium or both titanium and tungsten are selectively wet etched using NH₄OH and H₂O₂ in a ratio of 1:2, respectively. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using 305 grams of potassium ferricyanide (K₃Fe(CN)₆), 44.5 grams of sodium hydroxide (NaOH) and 1000 ml of water (H₂O). In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), HNO₃, sulfuric acid (H₂SO₄), HF, and H₂O₂. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using HF, HNO₃ and acetic acid (AcOH) in a ratio of 4:4:3, respectively. In one embodiment, the second pillars 132 and pillars 112 are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the second pillars 132 and pillars 112 are selectively dry etched using chlorine, fluorine, bromine or any combination thereof based chemistries. In one embodiment, the second pillars 132 and pillars 112 are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO₃ in a ratio of 3:1, respectively. In one embodiment, the second pillars 132 and pillars 112 are selectively etched using alkali with oxidizers (potassium nitrate (KNOB) and lead dioxide (PbO₂)). In one embodiment, the liner 108 is selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing.

Referring to FIG. 18, a first conductive material 140 is continuously and conformally deposited in the capacitor memory holes 138 and on the top surface 141 of the fourth dielectric material. The first conductive material 140 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The first conductive material 140 may be any suitable material known to the skilled artisan. In one or more embodiments, the first conductive material 140 comprises one or more of metal mode titanium (MMTi), metal silicide, or highly doped poly-silicon.

As illustrated in FIG. 18, in one or more embodiments, an overburden 142 of the first conductive material 140 is formed on the top surface 141 of the fourth dielectric material 134. Referring to FIG. 19A, the overburden 142 of the first conductive material 140 formed on the top surface 141 of the fourth dielectric material 134 may be removed by any suitable technique known to one of skill in the art including, but not limited to, chemical mechanical planarization (CMP), dry etching, or wet etching. In one or more embodiments, when the overburden 142 of the first conductive material 140 formed on the top surface 141 of the fourth dielectric material 134 is completely removed, the first conductive material 140 is substantially coplanar with the top surface 141 of the fourth dielectric material 134. Without intending to be by bound by theory, it is believed that, with the complete removal of the overburden 142, each capacitor memory hole 138 will be formed into one memory capacitor.

Referring to FIG. 19B, in one or more embodiments, the overburden 142 of the first conductive material 140 formed on the top surface 141 of the fourth dielectric material 134 is partially removed to partially separate the first conductive material 140. Without intending to be bound by theory, it is believed that, in this circumstance, the total capacitor for one memory cell will be made by more than one adjacent capacitor memory hole 138.

Referring to FIG. 20, a third dielectric material 144 is conformally deposited in the capacitor memory holes 138 on the first conductive material 140. The third dielectric material 144 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The third dielectric material 144 may be any suitable material known to the skilled artisan. In one or more embodiments, the third dielectric material 144 comprises a high-κ dielectric. In one or more embodiments, the third dielectric material 144 comprises a high-κ dielectric selected from one or more of aluminum oxide, hafnium oxide, or aluminum hafnium oxide (AlHfOx).

Referring to FIG. 21, in one or more embodiments a second conductive material 146 is deposited on the third dielectric material 144 to form a DRAM capacitor. The second conductive material 146 may be deposited by any deposition method known to one of skill in the art, including, but not limited to, ALD, CVD, or PVD. The second conductive material 126 may be any suitable material known to the skilled artisan. In one or more embodiments, the second conductive material 146 comprises one or more of poly-silicon, highly doped poly-silicon, metal, or metal silicide. In one or more embodiments, the capacitor bottom contact 104 is self-aligned with the first conductive material 140.

Referring to FIG. 21, one or more embodiments provide a DRAM capacitor comprising: a capacitor bottom contact 104 and a first dielectric material 102 on a substrate. A second dielectric material 114 is on the first dielectric material 102. A fourth dielectric material 134 is on the second dielectric material 114. A capacitor memory channel 138 is formed through the fourth dielectric material 134, the second dielectric material 114, and the first dielectric material 102. A capacitor 150 is formed in the capacitor memory channel 138. The capacitor 150 is self-aligned with the capacitor bottom contact 104. In one or more embodiments, the capacitor 150 comprises a first conductive material 140, a third dielectric material 144 on the first conductive material 140, and a second conductive material 146 on the third dielectric material 144. In one or more embodiments, the capacitor 150 has a top and a bottom, and a critical dimension of the top is substantially the same as a critical dimension of the bottom.

Processes may generally be stored in the memory of the system controller 990 as a software routine that, when executed by the processor, causes the process chamber to perform processes of the present disclosure. The software routine may also be stored and/or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the method of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The use of the terms “a” and “an” and “the” and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents. 

What is claimed is:
 1. A DRAM capacitor comprising: a capacitor bottom contact and a first dielectric material on a substrate; a second dielectric material on the first dielectric material; a fourth dielectric material on the second dielectric material; a capacitor memory channel formed through the fourth dielectric material, the second dielectric material, and the first dielectric material; and a capacitor formed in the capacitor memory channel, wherein the capacitor is self-aligned with the capacitor bottom contact.
 2. The DRAM capacitor of claim 1, wherein the capacitor comprises a first conductive material, a third dielectric material on the first conductive material, and a second conductive material on the third dielectric material.
 3. The DRAM capacitor of claim 1, wherein the capacitor has a top and a bottom, and a critical dimension of the top is substantially the same as a critical dimension of the bottom.
 4. The DRAM capacitor of claim 1, wherein the first dielectric material and the second dielectric material independently comprise one or more of silicon oxide and silicon nitride.
 5. The DRAM capacitor of claim 1, wherein the capacitor bottom contact comprises one or more of a metal, a metal silicide, poly-silicon, and EPI-silicon.
 6. The DRAM capacitor of claim 2, wherein the first conductive material comprises one or more of metal mode titanium (MMTi), metal silicide, and highly doped poly-silicon.
 7. The DRAM capacitor of claim 2, wherein the third dielectric material comprises a high-κ dielectric selected from one or more of aluminum oxide, hafnium oxide, and aluminum hafnium oxide (AlHfOx).
 8. The DRAM capacitor of claim 2, wherein the second conductive material comprises one or more of poly-silicon, metal, and metal silicide. 